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1 fn7288.4 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2002-2005, 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. el7457 40mhz non-inverting quad cmos driver the el7457 is a high speed, non-inverting, quad cmos driver. it is capable of running at clock rates up to 40mhz and features 2a peak drive capability and a nominal on-resistance of just 3 . the el7457 is ideal for driving highly capacitive loads, such as storage and vertical clocks in ccd applications. it is also well suited to ate pin driving, level-shifting, and clock-driving applications. the el7457 is capable of running from single or dual power supplies while using ground referenced inputs. each output can be switched to either the high (v h ) or low (v l ) supply pins, depending on the related input pin. the inputs are compatible with both 3v and 5v cmos and ttl logic. the output enable (oe) pin can be used to put the outputs into a high-impedance state. this is especially useful in ccd applications, where the driver should be disabled during power down. the el7457 also features very fast rise and fall times which are matched to within 1ns. the propagation delay is also matched between rising and falling edges to within 2ns. the el7457 is available in 16-pin qsop, 16-pin so (0.150"), and 16-pin qfn packages. all are specified for operation over the full -40c to +85c temperature range. pinouts features ? clocking speeds up to 40mhz ? 4 channels ? 12ns t r /t f at 1000pf c load ? 1ns rise and fall time match ? 1.5ns prop delay match ? low quiescent current - <1ma ? fast output enable function - 12ns ? wide output voltage range ?8v v l -5v ?-2v v h 16.5v ? 2a peak drive ?3 on resistance ? input level shifters ? ttl/cmos input-compatible ? pb-free (rohs compliant) applications ? ccd drivers ? digital cameras ? pin drivers ? clock/line drivers ? ultrasound transducer drivers ? ultrasonic and rf generators ? level shifting 1 2 3 4 16 15 14 13 5 6 7 12 11 10 8 9 1 2 3 4 12 11 10 9 5 6 7 8 16 15 14 13 inb vl vl gnd inc ind vs- outd oe ina vs+ outa outb vh vh outc thermal pad* ina oe inb vl gnd nc inc ind vs+ outa outb nc vh outc outd vs- el7457 [16-pin so (0.150?), qsop (0.150?)] top view el7457 [16-pin qfn (4x4mm)] top view * thermal pad connected to pin 7 (v s -) data sheet january 26, 2012
2 fn7288.4 january 26, 2012 ordering information part number (notes 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # el7457cuz 7457cuz -40c to +85c 16 ld qsop (0.150?) mdp0040 el7457cuz-t13 (note 1) 7457cuz -40c to +85c 16 ld qsop (0.150?) mdp0040 el7457cuz-t7 (note 1) 7457cuz -40c to +85c 16 ld qsop (0.150?) mdp0040 el7457cuz-t7a (note 1) 7457cuz -40c to +85c 16 ld qsop (0.150?) mdp0040 el7457csz el7457csz -40c to +85c 16 ld so (0.150?) mdp0027 el7457csz-t13 (note 1) el7457csz -40c to +85c 16 ld so (0.150?) mdp0027 el7457csz-t7 (note 1) el7457csz -40c to +85c 16 ld so (0.150?) mdp0027 el7457csz-t7a (note 1) el7457csz -40c to +85c 16 ld so (0.150?) mdp0027 el7457clz 7457clz -40c to +85c 16 ld qfn (4x4mm) l16.4x4h el7457clz-t13 (note 1) 7457clz -40c to +85c 16 ld qfn (4x4mm) l16.4x4h el7457clz-t7 (note 1) 7457clz -40c to +85c 16 ld qfn (4x4mm) l16.4x4h EL7457CLZ-T7A (note 1) 7457clz -40c to +85c 16 ld qfn (4x4mm) l16.4x4h notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs complian t and compatible with both snpb and pb-free soldering operation s). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std -020. 3. for moisture sensitivity level (msl), please see device information page for el7457 . for more information on msl please see tech brief tb363 . el7457
3 fn7288.4 january 26, 2012 absolute maxi mum ratings (t a = 25c) thermal information supply voltage (v s + to v s -) . . . . . . . . . . . . . . . . . . . . . . . . . . .+18v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . v s - -0.3v, v s + +0.3v continuous output current . . . . . . . . . . . . . . . . . . . . . . . . . . 100ma storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c thermal resistance ja (c/w) jc (c/w) 16 ld qfn (notes 4, 5) . . . . . . . . . . . . 43 5 16 ld soic (notes 6, 7). . . . . . . . . . . . 73 45 16 ld qsop (note 6). . . . . . . . . . . . . . 112 n/a ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. ja is measured with the component mounted on a high effective t hermal conductivity test board in free air. see tech brief tb379 for details. 7. for jc , the ?case temp? location is taken at the package top center. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v s + = +5v, v s - = -5v, v h = +5v, v l = -5v, t a = 25c, unless otherwise specified. parameter description condition min (note 8) typ max (note 8) unit input v ih logic ?1? input voltage 2.0 v i ih logic ?1? input current v ih = 5v 0.1 10 a v il logic ?0? input voltage 0.8 v i il logic ?0? input current v il = 0v 0.1 10 a c in input capacitance 3.5 pf r in input resistance 50 m output r oh on resistance v h to outx i out = -100ma 4.5 6 r ol on resistance v l to outx i out = +100ma 4 6 i leak output leakage current v h = v s +, v l = v s -0.110a i pk peak output current source 2.0 a sink 2.0 a power supply i s power supply current inputs = v s +0.51.5ma switching characteristics t r rise time c l = 1000pf 13.5 ns t f fall time c l = 1000pf 13 ns t rf t r , t f mismatch c l = 1000pf 0.5 ns t d + turn-off delay time c l = 1000pf 12.5 ns t d - turn-on delay time c l = 1000pf 14.5 ns t dd t d-1 - t d-2 mismatch c l = 1000pf 2 ns t enable enable delay time 12 ns el7457
4 fn7288.4 january 26, 2012 t disable disable delay time 12 ns electrical specifications v s + = +5v, v s - = -5v, v h = +5v, v l = -5v, t a = 25c, unless otherwise specified. parameter description condition min (note 8) typ max (note 8) unit electrical specifications v s + = +15v, v s - = 0v, v h = +15v, v l = 0v, t a = 25c, unless otherwise specified parameter description condition min (note 8) typ max (note 8) unit input v ih logic ?1? input voltage 2.4 v i ih logic ?1? input current v ih = 5v 0.1 10 a v il logic ?0? input voltage 0.8 v i il logic ?0? input current v il = 0v 0.1 10 a c in input capacitance 3.5 pf r in input resistance 50 m output r oh on resistance v h to out i out = -100ma 3.5 5 r ol on resistance v l to out i out = +100ma 3 5 i leak output leakage current v h = v s +, v l = v s -0.110a i pk peak output current source 2.0 a sink 2.0 a power supply i s power supply current inputs = v s +0.82ma switching characteristics t r rise time c l = 1000pf 11 ns t f fall time c l = 1000pf 12 ns t rf t r , t f mismatch c l = 1000pf 1 ns t d + turn-off delay time c l = 1000pf 11.5 ns t d - turn-on delay time c l = 1000pf 13 ns t dd t d-1 - t d-2 mismatch c l = 1000pf 1.5 ns t enable enable delay time 12 ns t disable disable delay time 12 ns note: 8. compliance to datasheet limits is assured by one or mo re methods: production test, characterization and/or design. el7457
5 fn7288.4 january 26, 2012 typical performance curves figure 1. switch threshold vs supply voltage figure 2. quiescent supply current vs supply voltage figure 3. ?on? resistance vs supply voltag e figure 4. rise/fall time vs supply voltage figure 5. rise/fall time vs temperature fig ure 6. propagation delay vs supply voltage t=25c high limit=2.4v low limit=0.8v hysteresis 1.8 1.6 1.4 1.2 1 5 7 10 12 15 supply voltage (v) input voltage (v) t=25c all inputs=0 all inputs=v s + 2 1.6 1.2 0.8 0 5 7 10 12 15 supply voltage (v) supply current (v) 0.4 i out =100ma t=25c v l to out 9 8 6 4 2 5 7 10 12 15 supply voltage (v) ?on? resistance ( ) 3 7 5 v h to out c l =1000pf t=25c 25 20 15 10 5 5 7 10 12 15 supply voltage (v) rise/fall time (ns) t f t r c l =1000pf v s +=15v 16 14 12 8 6 -50 0 50 100 125 temperature (c) rise/fall time (ns) t f t r 10 25 75 -25 c l =1000pf 25 20 15 5 51015 supply voltage (v) delay time (ns) 10 12 7 t d2 t d1 el7457
6 fn7288.4 january 26, 2012 figure 7. propagation delay vs temperature figure 8. rise/fall time vs load figure 9. supply current per channel vs capacitive load typical performance curves (continued) c l =1000pf v s +=15v 18 14 12 8 6 -50 0 50 100 125 temperature (c) delay time (ns) 10 25 75 -25 16 t d2 t d1 v s +=15v 140 120 100 20 0 100 1k 4.7k 10k load capacitance (pf) rise/fall time (ns) t f t r 60 2.2k 470 80 40 v s +=v h =10v v s -=v l =0v f=100khz 12 8 6 2 0 100 1k 10k load capacitance (pf) supply current (ma) 4 10 el7457
7 fn7288.4 january 26, 2012 timing diagram standard test configuration (cs/cu) table 1. nominal operating voltage range pin min max v s + to v s - 5v 16.5v v s - to gnd -5v 0v v h v s - + 2.5v v s + v l v s -v s + v h to v l 0v 16.5v v l to v s -0v 8v 90% 10% output 2.5v 5v input 0 t d + t r t d - t f 1 2 3 4 16 15 14 13 5 6 7 12 11 10 8 9 4.7f 0.1f ina inb vl inc ind 10k vs+ en vs- outd outc vh outb outa vs+ 0.1f 4.7f 1000pf 1000pf 0.1f 4.7f 1000pf 1000pf 0.1f 4.7f el7457
8 fn7288.4 january 26, 2012 pin descriptions 16-pin qsop (0.150?), so (0.150?) 16-pin qfn (4x4mm) name function equivalent circuit 1 15 ina input channel a circuit 1 2 16 oe output enable (reference circuit 1) 3 1 inb input channel b (reference circuit 1) 4 2, 3 vl low voltage input pin 5 4 gnd input logic ground 6, 13 nc no connection 7 5 inc input channel c (reference circuit 1) 8 6 ind input channel d (reference circuit 1) 9 7 vs- negative supply voltage 10 8 outd output channel d circuit 2 11 9 outc output channel c (reference circuit 2) 12 10, 11 vh high voltage input pin 14 12 outb output channel b (reference circuit 2) 15 13 outa output channel a (reference circuit 2) 16 14 vs+ positive supply voltage v s - v s - v s + v s + input v s - v s + output v s - v l v h el7457
9 fn7288.4 january 26, 2012 block diagram applications information product description the el7457 is a high performance 40mhz high speed quad driver. each channel of the el7457 consists of a single p-channel high side driver and a single n-channel low side driver. these 3 devices will pull the output (out x ) to either the high or low voltage, on v h and v l respectively, depending on the input logic signal (in x ). it should be noted that there is only one set of high and low voltage pins. a common output enable (oe) pin is available on the el7457. this pin, when pulled low will put all outputs in to the high impedance state. the el7457 is available in 16-pin so (0.150"), 16-pin qsop, and ultra-small 16-pin qfn packages. the relevant package should be chosen depending on the calculated power dissipation. supply voltage range and input compatibility the el7457 is designed for operation on supplies from 5v to 15v with 10% tolerance (i.e. 4.5v to 18v). the table on page 6 shows the specifications for the relationship between the v s +, v s -, v h , v l , and gnd pins. the el7457 does not contain a true analog switch and therefore v l should always be less than v h . all input pins are compatible with both 3v and 5v cmos signals with a positive supply (v s +) of 5v, the el7457 is also compatible with ttl inputs. power supply bypassing when using the el7457, it is very important to use adequate power supply bypassing. the high switching currents developed by the el7457 necessitate the use of a bypass capacitor on both the positive and negative supplies. it is recommended that a 4.7f tantalum capacitor be used in parallel with a 0.1f low-inductance ceramic mlc capacitor. these should be placed as close to the supply pins as possible. it is also recommended that the v h and v l pins have some level of bypassing, especially if the el7457 is driving highly capacitive loads. power dissipation calculation when switching at high speeds, or driving heavy loads, the el7457 drive capability is limited by the rise in die temperature brought about by in ternal power dissipation. for reliable operation die temper ature must be kept below t jmax (125c). it is necessary to calculate the power dissipation for a given application prior to selecting package type. power dissipation may be calculated: where: v s is the total power supply to the el7457 (from v s + to v s -) v out is the swing on the output (v h - v l ) c l is the load capacitance c int is the internal load capacitance (80pf max) i s is the quiescent supply current (3ma max) f is frequency having obtained the application?s power dissipation, the maximum junction temperature can be calculated: where: t jmax is the maximum junction temperature (125c) t max is the maximum ambient operating temperature pd is the power dissipation calculated above ja is the thermal resistance, junction to ambient, of the application (package + pcb combination). refer to the package power dissipation curves on page 6. 3-state control level shifter output v l v h oe input v s + gnd v s - pd v s i s () c int v s 2 f () c l v out 2 f () + 1 4 + = (eq. 1) t jmax t max ja pd + = (eq. 2) el7457
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7288.4 january 26, 2012 el7457 quarter size outline plast ic packages family (qsop) 0.010 c a b seating plane detail x e e1 1 (n/2) (n/2)+1 n pin #1 i.d. mark b 0.004 c c a see detail "x" a2 44 gauge plane 0.010 l a1 d b h c e a 0.007 c a b l1 mdp0040 quarter size outline plastic packages family symbol inches tolerance notes qsop16 qsop24 qsop28 a 0.068 0.068 0.068 max. - a1 0.006 0.006 0.006 0.002 - a2 0.056 0.056 0.056 0.004 - b 0.010 0.010 0.010 0.002 - c 0.008 0.008 0.008 0.001 - d 0.193 0.341 0.390 0.004 1, 3 e 0.236 0.236 0.236 0.008 - e1 0.154 0.154 0.154 0.004 2, 3 e 0.025 0.025 0.025 basic - l 0.025 0.025 0.025 0.009 - l1 0.041 0.041 0.041 basic - n 16 24 28 reference - rev. f 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994.
11 fn7288.4 january 26, 2012 el7457 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
12 fn7288.4 january 26, 2012 el7457 package outline drawing l16.4x4h 16 lead quad flat no-lead plastic package rev 0, 1/12 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view see detail "x" 0.30 0.05 base plane pin #1 5 8 ( 3 . 6 typ ) (12x0.65) (16x0.30) 0 . 20 ref +0.03/-0.02 c 5 4 0.10 c m index area (4x) 0.15 pin 1 6 4.00 12 4.00 9 a b 4 0.65 12x 13 4x 1.95 16 1 6 c seating plane 0.10 c ab 16x 0.5500.05 2.40 ( 2.40) 0.900.10 (16x0.75) 2.40 index area

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